MIPS Processor

Member: Shingo Morita
Tools: Vivado, Verilog, MIPS

Description

In this project, I designed a MIPS processor using Verilog on Vivado. The flow of the design went from Single Cycle, Multi-Cycle, and Pipeline. In this assignment, I learned how the program is interpreted at the hardware level. Additionally, I also learned the Pros and Cons of each of the implementations.

Single Cycle Processor

Characteristics:

Longest instruction limits the cycle time, which leads to a long Cycle time.
The cycle time is too long for many of the instructions except for the LOAD.
So, the efficiency of the processor is very low.

Use Case: Simple designs where simplicity is more important than performance.

Multi-Cycle Processor

Characteristics:

It divides instruction into smaller steps and executes each step in one cycle.
Therefore, the cycle time decreases because it is limited by the longest step.
It does not always perform better than the Single Cycle because of the setup time between each Cycle.
However, it is much more efficient in terms of resources because it can use elements like the adder that was used in previous steps.

Advantages:

Better resource utilization
Shorter cycle time
More flexible instruction handling

Trade-offs:

Additional control complexity
Setup time overhead between cycles

Pipeline Processor

Characteristics:

It divides all instructions into multiple stages.
In each stage, one instruction is loaded and passed to the next stage per cycle.
Theoretically, it can execute one instruction per cycle.
However, it requires stalls in some instructions the Number of instructions per cycle is usually less than 1.
Although this seems like we can decrease the time it takes to execute infinitely by adding a pipeline, It also has a limit on a number of pipelines it could have.
As the pipeline requires to set up time, the number of pipelines is limited by (SetUp Time) * (number of pipelines) < Time To execute one instruction.

Advantages:

Highest theoretical throughput
Better instruction-level parallelism
Efficient resource utilization

Limitations:

Pipeline hazards (data, control, structural)
Setup time constraints limit maximum pipeline depth
Complexity in hazard detection and resolution

Key Learnings

Hardware-Software Interface: Understanding how high-level programs translate to hardware operations provides deep insight into computer architecture.
Performance Trade-offs: Each processor design represents a different balance between simplicity, performance, and resource utilization.
Design Evolution: Progressing from Single Cycle to Pipeline demonstrates how architectural improvements address performance bottlenecks.
Resource Efficiency: Multi-cycle processors show how resource sharing can improve efficiency without the complexity of pipelining.
Theoretical vs. Practical Performance: Pipeline processors demonstrate the gap between theoretical maximum performance and practical performance due to hazards and stalls.

Technical Details

Design Tools

Vivado: Used for synthesis, simulation, and implementation
Verilog: Hardware description language for processor design
MIPS Architecture: 32-bit RISC instruction set architecture

Design Process

Single Cycle Design: Baseline implementation with simple control logic
Multi-Cycle Design: Added state machine for instruction execution phases
Pipeline Design: Implemented 5-stage pipeline with hazard detection

Challenges Encountered

Timing Constraints: Ensuring all paths meet timing requirements
Hazard Resolution: Implementing forwarding and stalling mechanisms in pipeline
Control Logic Complexity: Managing increasingly complex control units across designs
Resource Sharing: Optimizing resource utilization in multi-cycle design

Future Improvements

Advanced branch prediction for pipeline
Out-of-order execution capabilities
Cache integration
Superscalar design
Performance analysis and optimization